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Preliminary Technical Data

DSP Microcomputer

This information applies to a product under development. Its characteristics and speci-
fications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise agreed to in
writing.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 www.analog.com
Fax:781/326-8703

©Analog Devices,Inc., 2002

REV. PrB

PRELIMINARY TECHNICAL DATA

ADSP-21160N

SUMMARY
High-Performance 32-Bit DSP--Applications in Audio,

Medical, Military, Graphics, Imaging, and
Communication

Super Harvard Architecture--Four Independent Buses

for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O

Backwards-Compatible--Assembly Source Level

Compatible with Code for ADSP-2106x DSPs

Single-Instruction-Multiple-Data (SIMD) Computational

Architecture--Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File

Integrated Peripherals--Integrated I/O Processor,

4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)

KEY FEATURES
95 MHz (10.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD

Operations in Both Computational Units

570 MFLOPS Peak and 380 MFLOPS Sustained

Performance (Based on FIR)

Dual Data Address Generators (DAGs) with Modulo and

Bit-Reverse Addressing

Zero-Overhead Looping and Single-Cycle Loop Setup,

Providing Efficient Program Sequencing

IEEE 1149.1 JTAG Standard Test Access Port and

On-Chip Emulation

400-Ball 27

27 mm Metric PBGA Package

FUNCTIONAL BLOCK DIAGRAM

MULT

ALU

BARREL
SHIFTER

DATA

REGISTER

FILE

(PEY)

16 X 40-BIT

MULT

ALU

BARREL

SHIFTER

DATA

REGISTER

FILE

(PEX)

16 X 40-BIT

SERIAL PORTS

(2)

LINK PORTS

(6)

IOP

REGISTERS

(MEMORY

MAPPED)

CONTROL,

STATUS, AND

DATA BUFFERS

I/O PROCESSOR

DMA

CONTROLLER

TIMER

INSTRUCTION

CACHE

32 X 48-BIT

ADDR

DATA

ADDR

DATA

ADDR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT

I/O PORT

DUAL-PORTED SRAM

JTAG

TEST AND

EMULATION

HOST PORT

ADDR BUS

MUX

IOA

IOD

MULTIPROCESSOR

INTERFACE

EXTERNAL

PORT

DATA BUS

MUX

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DAG1

8X4X32

16/32/40/48/64

32/40/64

CORE PROCESSOR

PROGRAM

SEQUENCER

DAG2

8X4X32

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)

Architecture Provides:
Two Computational Processing Elements
Concurrent Execution--Each Processing Element

Executes the Same Instruction, but Operates on
Different Data

Code Compatibility--at Assembly Level, Uses the

Same Instruction Set as the ADSP-2106x
SHARC DSPs

Parallelism in Buses and Computational Units Allows:

Single-cycle Execution (with or without SIMD) of: A

Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch

Transfers Between Memory and Core at up to Four

32-Bit Floating- or Fixed-Point Words per Cycle

Accelerated FFT Butterfly Computation Through a

Multiply with Add and Subtract

4M Bits On-Chip Dual-Ported SRAM for Independent

Access by Core Processor, Host, and DMA

DMA Controller supports:

14 Zero-Overhead DMA Channels for Transfers Between

ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports

64-Bit Background DMA Transfers at Core Clock Speed,

in Parallel with Full-Speed Processor Execution

665M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit

Microprocessors

4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State

Generation and Page-Mode for Off-Chip Memory

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of up to Six ADSP-21160Ns plus Host

Six Link Ports for Point-To-Point Connectivity and Array

Multiprocessing

Serial Ports Provide:

Two 47.5M Bits/s Synchronous Serial Ports with

Companding Hardware

Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM

External Memories

Up to 47.5 MHz Operation

GENERAL DESCRIPTION

The ADSP-21160N SHARC DSP is the second iteration
of the ADSP-21160. Built in a 0.18 micron CMOS process,
it offers higher performance and lower power consumption
than its predecessor, the ADSP-21160M. Easing portabil-
ity, the ADSP-21160N is application source code
compatible with first generation ADSP-2106x SHARC
DSPs in SISD (Single Instruction, Single Data) mode. To
take advantage of the processor's SIMD (Single Instruction,
Multiple Data) capability, some code changes are needed.
Like other SHARCs, the ADSP-21160N is a 32-bit
processor that is optimized for high performance DSP appli-
cations. The ADSP-21160N includes an 95 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor
with multiprocessing support, and multiple internal buses
to eliminate I/O bottlenecks.

The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160N can double performance versus the
ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160N has a 10.5 ns instruc-
tion cycle time. With its SIMD computational hardware
running at 95 MHz, the ADSP-21160N can perform 570
million math operations per second.

Table 1

shows performance benchmarks for the

ADSP-21160N.

These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices's
website.

The ADSP-21160N continues SHARC's industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M-bit dual
ported SRAM memory, host processor interface, I/O

Table 1. ADSP-21160N Benchmarks

Benchmark Algorithm

Speed

1024 Point Complex FFT (Radix 4, with
reversal)

96 µs

FIR Filter (per tap)

5.25 ns

IIR Filter (per biquad)

21 ns

Matrix Multiply (pipelined)
[3 3] [3 1]

47.25 ns

Matrix Multiply (pipelined)
[4 4] [4 1]

84 ns

Divide (y/x)

31.5 ns

Inverse Square Root

47.25 ns

DMA Transfer Rate

665M Bytes/s

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.

The functional block diagram

on page 1

shows a block

diagram of the ADSP-21160N, illustrating the following
architectural features:

Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register File

Data Address Generators (DAG1, DAG2)

Program sequencer with instruction cache

PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle

Interval timer

On-Chip SRAM (4M bits)

External port that supports:

Interfacing to off-chip memory peripherals

Glueless multiprocessing support for six
ADSP-21160N SHARCs

Host port

DMA controller

Serial ports and link ports

JTAG test access port

Figure 1

shows a typical single-processor system. A multi-

processing system appears in

Figure 4

ADSP-21160N Family Core Architecture

The ADSP-21160N includes the following archi-
tectural features of the ADSP-2116x family core. The
ADSP-21160N is code compatible at the assembly level
with the ADSP-2106x and ADSP-21161.

SIMD Computational Engine

The ADSP-21160N contains two computational process-
ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational
units. The computational units consist of an arith-
metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz-
ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera-
tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com-
putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter-
mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0R15 and in PEY
as S0S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21160N features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc-
tions and data (see the functional block diagram

on page 1

Figure 1. Single-Processor System

RESET

JTAG

ADSP-21160

BMS

CLOCK

LINK

DEVICES

(6 MAX)

(OPTIONAL)

BOOT

EPROM

(OPTIONAL)

ADDR

MEMORY/

MAPPED
DEVICES

(OPTIONAL)

DATA

DMA DEVICE

(OPTIONAL)

DATA

ADDR

DATA

HOST

PROCESSOR

INTERFACE
(OPTIONAL)

RDx

PAGE

CLKOUT

ACK

BR16

DMAR12

CLKIN

IRQ20

LXCLK

TCLK0

RPBA

CLK_CFG30

EBOOT

LBOOT

FLAG30

TIMEXP

LXACK

LXDAT70

DR0

DT0

RSF0

TFS0

RCLK0

TCLK1

DR1

DT1

RSF1

TFS1

RCLK1

ID20

SERIAL
DEVICE

(OPTIONAL)

SERIAL
DEVICE

(OPTIONAL)

REDY

HBG

HBR

DMAG12

SBTS

MS30

WRx

DATA630

DATA

ADDR

ACK

ADDR310

CIF

BRST

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

With the ADSP-21160N's separate program and data
memory buses and on-chip instruction cache, the processor
can simultaneously fetch four operands and an instruction
(from the cache), all in a single cycle.

Instruction Cache

The ADSP-21160N includes an on-chip instruction cache
that enables three-bus operation for fetching an instruction
and four data values. The cache is selective--only the
instructions whose fetches conflict with PM bus data
accesses are cached. This cache allows full-speed execution
of core, providing looped operations such as digital filter
multiply- accumulates and FFT butterfly processing.

Data Address Generators with Hardware
Circular Buffers

The ADSP-21160N's two data address generators (DAGs)
are used for indirect addressing and provide for implement-
ing circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data struc-
tures required in digital signal processing, and are
commonly used in digital filters and Fourier transforms.
The two DAGs of the ADSP-21160N contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs auto-
matically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying imple-
mentation. Circular buffers can start and end at any
memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example,
the ADSP-21160N can conditionally execute a multiply, an
add, and subtract, in both processing elements, while
branching, all in a single instruction.

ADSP-21160N Memory and I/O Interface Features

Augmenting the ADSP-2116x family core, the
ADSP-21160N adds the following architectural features:

Dual-Ported On-Chip Memory

The ADSP-21160N contains four megabits of on-chip
SRAM, organized as two blocks of 2M bits each, which can
be configured for different combinations of code and data
storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O proces-
sor. The dual-ported memory in combination with three
separate on-chip buses allows two data transfers from the
core and one from I/O processor, in a single cycle. On the
ADSP-21160N, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of
16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four
megabits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the
amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point
formats is done in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data, using the DM
bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and
PM bus in this way, with one dedicated to each memory
block, assures single-cycle execution with two data trans-
fers. In this case, the instruction must be available in
the cache.

Off-Chip Memory and Peripherals Interface

The ADSP-21160N's external port provides the processor's
interface to off-chip memory and peripherals. The 4G word
off-chip address space is included in the ADSP-21160N's
unified address space. The separate on-chip buses--for PM
addresses, PM data, DM addresses, DM data, I/O
addresses, and I/O data--are multiplexed at the external
port to create an external system bus with a single 32-bit
address bus and a single 64-bit data bus. The lower 32 bits
of the external data bus connect to even addresses and the
upper 32 bits of the 64 connect to odd addresses. Every
access to external memory is based on an address that
fetches a 32-bit word, and with the 64-bit bus, two address
locations can be accessed at once. When fetching an instruc-
tion from external memory, two 32-bit data locations are
being accessed (16 bits are unused).

Figure 3

shows the

alignment of various accesses to external memory.

The external port supports asynchronous, synchronous,
and synchronous burst accesses. ZBT synchronous burst
SRAM can be interfaced gluelessly. Addressing of external
memory devices is facilitated by on-chip decoding of
high-order address lines to generate memory bank select
signals. Separate control lines are also generated for simpli-
fied addressing of page-mode DRAM. The ADSP-21160N
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold, and
disable time requirements.

DMA Controller

The ADSP-21160N's on-chip DMA controller allows
zero-overhead data transfers without processor interven-
tion. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the
ADSP-21160N's internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the ADSP-21160N's internal memory
and its serial ports or link ports. External bus packing to
16-, 32-, 48-, or 64-bit words is performed during DMA
transfers. Fourteen channels of DMA are available on the
ADSP-21160N--six via the link ports, four via the serial
ports, and four via the processor's external port (for either
host processor, other ADSP-21160Ns, memory or I/O

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

transfers). Programs can be downloaded to the
ADSP-21160N using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (

DMAR12, DMAG12).

Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-21160N offers powerful features tailored to
multiprocessing DSP systems as shown in

Figure 4

. The

external port and link ports provide integrated glueless mul-
tiprocessing support.

The external port supports a unified address space (see

Figure 2

) that allows direct interprocessor accesses of each

ADSP-21160N's internal memory. Distributed bus arbitra-
tion logic is included on-chip for simple, glueless connection
of systems containing up to six ADSP-21160Ns and a host
processor. Master processor changeover incurs only one
cycle of overhead. Bus arbitration is selectable as either fixed
or rotating priority. Bus lock allows indivisible read-mod-

ify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 380M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ns and can be used
to implement reflective semaphores.

Six link ports provide for a second method of multiprocess-
ing communications. Each link port can support
communications to another ADSP-21160N. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.

Link Ports

The ADSP-21160N features six 8-bit link ports that provide
additional I/O capabilities. With the capability of running
at 95 MHz rates, each link port can support 95M bytes/s.
Link port I/O is especially useful for point-to-point inter-
processor communication in multiprocessing systems. The
link ports can operate independently and simultaneously.
Link port data is packed into 48- or 32-bit words, and can
be directly read by the core processor or DMA-transferred
to on-chip memory. Each link port has its own double-buff-
ered input and output registers. Clock/acknowledge
handshaking controls link port transfers. Transfers are pro-
grammable as either transmit or receive.

Serial Ports

The ADSP-21160N features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
each with a maximum data rate of 47.5M bit/s. Independent
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-

Figure 2. ADSP-21160N Memory Map

0x00 0000

0x02 0000

0x04 0000

0x08 0000

0x10 0000

0x20 0000

0x30 0000

0x40 0000

0x50 0000

0x60 0000

0x70 0000

0x7F FFFF

0x80 0000

0xFFFF FFFF

Internal
Memory
Space

External
Memory
Space

IOP Reg's

Long Word

Normal Word

Short Word

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Broadcast

All DSPs

Bank 0

Bank 1

Bank 2

Bank 3

Nonbanked

Memory

(ID = 011)

(ID = 100)

Memory

(ID = 101)

Memory

(ID = 110)

Write to

(ID = 111)

Memory

(ID = 010)

Memory

(ID = 001)

Multiprocessor
Memory
Space

Figure 3. ADSP-21160N External Data Alignment

Options

DATA630

RDH

WRH

RDL

WRL

EPROM

16-BIT PACKED

32-BIT PACKED

64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION

64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH

RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:

64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS

BYTE 0

BYTE 7

32-BIT NORMAL WORD (EVEN ADDRESS)

32-BIT NORMAL WORD (ODD ADDRESS)

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit-
tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable

synchronization and transmit modes as well as optional
µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.

Host Processor Interface

The ADSP-21160N host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160N's external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M's external bus with host bus request
(

HBR), host but grant (HBG), ready (REDY), acknowledge

(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160N,
and can access the DMA channel setup and mailbox regis-
ters. Vector interrupt support provides efficient execution
of host commands.

Program Booting

The internal memory of the ADSP-21160N can be booted
at system power-up from an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the

BMS (Boot Memory Select),

EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.

Phased Locked Loop

The ADSP-21160N uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.

Power Supplies

The ADSP-21160N has separate power supply connections
for the internal (V

DDINT

), external (V

DDEXT

), and analog

(AV

/AGND) power supplies. The internal and analog

supplies must meet the 1.9 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.

The PLL Filter

Figure 5 on page 7

must be added for each

ADSP-21160N in the system. VDDint is the digital core
supply. It is recommended that the capacitors be connected
directly to AGND using short thick trace. It is recom-
mended that the capacitors be placed as close to AVDD and
AGND as possible. The connection from AGND to the
(digital) ground plane should be made after the capacitors.
The use of a thick trace for AGND is reasonable only
because the PLL is a relatively low power circuit - it does
not apply to any other ADSP-21160N GND connection.

Figure 4. Shared Memory Multiprocessing System

ADDR310

BMS

ADSP-21160#1

CONTROL

ADSP-21160#2

ADDR310

CONTROL

ADSP-21160#3

ID20

RESET

RPBA

CLKIN

ID20

RESET

RPBA

ID20

RESET

RPBA

CLKIN

ADSP-21160#6
ADSP-21160#5
ADSP-21160#4

CLOCK

RESET

ADDR

DATA

HOSTPROCESSOR
INTERFACE(OPTIONAL)

ACK

GLOBALMEMORY
AND
PERIPHERAL(OPTIONAL)

ADDR

DATA

ADDR

DATA

BOOTEPROM(OPTIONAL)

RDx

MS30

SBTS

CLKOUT

ACK

ADDR310

CLKIN

001

PAGE

010

011

BR1

BR26

REDY

HBG

HBR

WRx

DATA630

BR12

BR46

BR3

DATA630

BR1

BR36

BR2

DATA630

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Development Tools

The ADSP-21160N is supported with a complete set of
software and hardware development tools, including Analog
Devices' emulators and VisualDSP++

development envi-

ronment. The same emulator hardware that supports other
ADSP-2116x DSPs, also fully emulates the
ADSP-21160N.

The VisualDSP++ project management environment lets
programmers develop and debug an application. This envi-
ronment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simula-
tor, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. Two key points
for these tools are:

Compiled ADSP-2116x C/C++ code efficiency--the
compiler has been developed for efficient translation of
C/C++ code to ADSP-2116x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.

ADSP-2106x family code compatibility--The assembler
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-2116x.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

View mixed C/C++ and assembly code (interleaved
source and object information)

Insert break points

Set conditional breakpoints on registers, memory, and
stacks

Trace instruction execution

Perform linear or statistical profiling of program
execution

Fill, dump, and graphically plot the contents of memory

Source level debugging

Create custom debugger windows

The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all

of the ADSP-2116x development tools, including the syntax
highlighting in the VisualDSP++ editor. This capability
permits:

Control how the development tools process inputs and
generate outputs.

Maintain a one-to-one correspondence with the tool's
command line switches.

Analog Devices' DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21160N processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor's JTAG interface--the
emulator does not affect target system loading or timing.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-2116x processor
family. Hardware tools include ADSP-2116x PC plug-in
cards. Third Party software tools include DSP libraries,
real-time operating systems, and block diagram
design tools.

Designing an Emulator-Compatible DSP Board
(Target)

The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The
emulator uses the TAP to access the internal features of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers.
The DSP must be halted to send data and commands, but
once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on
system timing.

To use these emulators, the target's design must include the
interface between an Analog Devices' JTAG DSP and the
emulation header on a custom DSP target board.

Target Board Header

The emulator interface to an Analog Devices' JTAG DSP
is a 14-pin header, as shown in

Figure 6

. The customer must

supply this header on the target board in order to commu-
nicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on
0.1"

0.1" spacing, with a minimum post length of 0.235".

Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the
target board.

Figure 5. Analog Power (AV

) Filter Circuit

VisualDSP++ is a registered trademark of Analog Devices, Inc.

DDINT

AGND

0.01 F

0.1 F

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.

As can be seen in

Figure 6

, there are two sets of signals on

the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO,

TRST, and EMU used for emulation

purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and

BTRST that are option-

ally used for board-level (boundary scan) testing.

When the emulator is not connected to this header, place
jumpers across BTMS, BTCK,

BTRST, and BTDI as

shown in

Figure 7

. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.

JTAG Emulator Pod Connector

Figure 8

details the dimensions of the JTAG pod connector

at the 14-pin target end.

Figure 9

displays the keep-out area

for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.

Design-for-Emulation Circuit Information

For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website--use site search on

"EE-68" (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.

Additional Information

This data sheet provides a general overview of the
ADSP-21160N architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.

Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in
Place)

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

Figure 7. JTAG Target Board Connector with No Local

Boundary Scan

Figure 8. JTAG Pod Connector Dimensions

Figure 9. JTAG Pod Connector Keep-Out Area

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

0.64"

0.88"

0.24"

0.10"

0.15"

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTIONS

ADSP-21160N pin definitions are listed below. Inputs iden-
tified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for

TRST).

Tie or pull unused inputs to VDD or GND, except for the
following:

ADDR31 0, DATA63 0, PAGE, BRST, CLKOUT
(ID2 0 = 00x) (NOTE: These pins have a logic-level hold
circuit enabled on the ADSP-21160N DSP with ID2 0
= 00x)

PA, ACK, MS30, RDx, WRx, CIF, DMARx, DMAGx
(ID2 0 = 00x) (NOTE: These pins have a pull-up
enabled on the ADSP-21160N DSP with ID2 0 = 00x)

LxCLK, LxACK, LxDAT7 0 (LxPDRDE = 0) (NOTE:
See Link Port Buffer Control Register Bit definitions in
the ADSP-21160 DSP Hardware Reference).

DTx, DRx, TCLKx, RCLKx,

EMU, TMS, TRST, TDI

(NOTE: These pins have a pull-up.)

The following symbols appear in the Type column of

Table 2

: A = Asynchronous, G = Ground, I = Input,

O = Output, P = Power Supply, S = Synchronous,
(A/D) = Active Drive, (O/D) = Open Drain, and
T = Three-State (when

SBTS is asserted, or when the

ADSP-21160N is a bus slave).

Table 2. Pin Function Descriptions

Pin

Type

Function

ADDR310

I/O/T

External Bus Address. The ADSP-21160N outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ns. The
ADSP-21160N inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP's
ADDR310 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160N with ID20 = 00x).

DATA630

I/O/T

External Bus Data. The ADSP-21160N inputs and outputs data and instructions on
these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP's DATA63-0 pins maintains the input at the level it was last driven (only enabled
on the ADSP-21160N with ID20 = 00x).

MS30

O/T

Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-
sponding banks of external memory. Memory bank size must be defined in the SYSCON
control register. The

MS30 outputs are decoded memory address lines. In asyn-

chronous access mode, the

MS30 outputs transition with the other address outputs.

In synchronous access modes, the

MS30 outputs assert with the other address lines;

however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted.
MS30 has a 20k

internal pull-up resistor that is enabled on the ADSP-21160N with

ID20 = 00x.

RDL

I/O/T

Memory Read Low Strobe.

RDL is asserted whenever ADSP-21160N reads from the

low word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert

RDL for reading from

the low word of ADSP-21160N internal memory. In a multiprocessing system,

RDL is

driven by the bus master.

RDL has a 20k

internal pull-up resistor that is enabled on

the ADSP-21160N with ID20 = 00x.

RDH

I/O/T

Memory Read High Strobe.

RDH is asserted whenever ADSP-21160N reads from the

high word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert

RDH for reading from

the high word of ADSP-21160N internal memory. In a multiprocessing system,

RDH

is driven by the bus master.

RDH has a 20k

internal pull-up resistor that is enabled

on the ADSP-21160N with ID20 = 00x.

WRL

I/O/T

Memory Write Low Strobe.

WRL is asserted when ADSP-21160N writes to the low

word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert

WRL for writing to ADSP-21160N's low word of internal memory. In a

multiprocessing system,

WRL is driven by the bus master. WRL has a 20k

internal

pull-up resistor that is enabled on the ADSP-21160N with ID20 = 00x.

REV. PrB

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ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

WRH

I/O/T

Memory Write High Strobe.

WRH is asserted when ADSP-21160N writes to the high

word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert

WRH for writing to ADSP-21160N's high word of internal memory. In a

multiprocessing system,

WRH is driven by the bus master. WRH has a 20k

internal

pull-up resistor that is enabled on the ADSP-21160N with ID20 = 00x.

PAGE

O/T

DRAM Page Boundary. The ADSP-21160N asserts this pin to signal that an external
DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160N's memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP's PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160N with ID20 = 00x).

BRST

I/O/T

Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160N, ADSP-21160N automatically increments the address
as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer.
It is asserted for every cycle after that, except for the last data request cycle (denoted by
RDx or WRx asserted and BRST negated). A keeper latch on the DSP's BRST pin
maintains the input at the level it was last driven (only enabled on the ADSP-21160N
with ID20 = 00x).

ACK

I/O/S

Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160N
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory. ACK has a 2k

internal pull-up resistor that is enabled on the ADSP-21160N

with ID20 = 00x.

SBTS

I/S

Suspend Bus and Three-State. External devices can assert

SBTS (low) to place the

external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21160N attempts to access external memory while

SBTS is asserted,

the processor will halt and the memory access will not be completed until

SBTS is

deasserted.

SBTS should only be used to recover from host processor and/or

ADSP-21160N deadlock or used with a DRAM controller.

IRQ20

I/A

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.

FLAG30

I/O/A

Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.

TIMEXP

Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and
TCOUNT decrements to zero.

HBR

I/A

Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160N's external bus. When

HBR is asserted in a multiprocessing system, the

ADSP-21160N that is bus master will relinquish the bus and assert

HBG. To relinquish

the bus, the ADSP-21160N places the address, data, select, and strobe lines in a high
impedance state.

HBR has priority over all ADSP-21160N bus requests (BR61) in a

multiprocessing system.

HBG

I/O

Host Bus Grant. Acknowledges an

HBR bus request, indicating that the host processor

may take control of the external bus.

HBG is asserted (held low) by the ADSP-21160N

until

HBR is released. In a multiprocessing system, HBG is output by the

ADSP-21160N bus master and is monitored by all others. After

HBR is asserted, and

before

HBG is given, HBG will float for 1 tCLK (1 CLKIN cycle). To avoid erroneous

grants,

HBG should be pulled up with a 20k to 50k ohm external resistor.

I/A

Chip Select. Asserted by host processor to select the ADSP-21160N.

Table 2. Pin Function Descriptions (Continued)

Pin

Type

Function

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

REDY

O (O/D)

Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add waitstates
to a host access when

CS and HBR inputs are asserted.

DMAR1

I/A

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services.

DMAR1 has a 20k

internal pull-up resistor that is enabled on the

ADSP-21160N with ID20 = 00x.

DMAR2

I/A

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services.

DMAR2 has a 20k

internal pull-up resistor that is enabled on the

ADSP-21160N with ID20 = 00x.

ID20

Multiprocessing ID. Determines which multiprocessing bus request (

BR1BR6) is used

by ADSP-21160N. ID = 001 corresponds to

BR1, ID = 010 corresponds to BR2, and

so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.

DMAG1

O/T

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.

DMAG1 has a

20k

internal pull-up resistor that is enabled on the ADSP-21160N with ID20 = 00x.

DMAG2

O/T

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.

DMAG2 has a

20k

internal pull-up resistor that is enabled on the ADSP-21160N with ID20 = 00x.

BR61

I/O/S

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate
for bus mastership. An ADSP-21160N only drives its own

BRx line (corresponding to

the value of its ID20 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ns, the unused

BRx pins should be pulled high; the processor's

own

BRx line must not be pulled high or low because it is an output.

RPBA

I/S

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160N. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160N.

I/O/T

Priority Access. Asserting its

PA pin allows an ADSP-21160N bus slave to interrupt

background DMA transfers and gain access to the external bus.

PA is connected to all

ADSP-21160Ns in the system. If access priority is not required in a system, the

PA pin

should be left unconnected.

PA has a 20k

internal pull-up resistor that is enabled on

the ADSP-21160N with ID20 = 00x.

DTx

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k

internal pull-up resistor.

DRx

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k

internal pull-up resistor.

TCLKx

I/O

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k

internal pull-up resistor.

RCLKx

I/O

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k

internal pull-up resistor.

TFSx

I/O

Transmit Frame Sync (Serial Ports 0, 1).

RFSx

I/O

Receive Frame Sync (Serial Ports 0, 1).

LxDAT70

I/O

Link Port Data (Link Ports 05). Each LxDAT pin has a 50 k

internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL01 register.

LxCLK

I/O

Link Port Clock (Link Ports 05). Each LxCLK pin has a 50 k

internal pull-down

resistor that is enabled or disabled by the LPDRD bit of the LCTL01 register.

LxACK

I/O

Link Port Acknowledge (Link Ports 05). Each LxACK pin has a 50 k

internal

pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT

EPROM Boot Select. For a description of how this pin operates, see

Table 3

. This signal

is a system configuration selection that should be hardwired.

LBOOT

Link Boot. For a description of how this pin operates, see

Table 3

. This signal is a system

configuration selection that should be hardwired.

BMS

I/O/T

Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see

Table 3

. This input is a system configuration selection that should be

hardwired.

Table 2. Pin Function Descriptions (Continued)

Pin

Type

Function

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

CLKIN

Local Clock In. CLKIN is the ADSP-21160N clock input. The ADSP-21160N external
port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the
CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.

CLK_CFG30

Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal
to n CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG30 inputs.
For clock configuration definitions, see the

RESET & CLKIN section of the System

Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.

CLKOUT

O/T

CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can
be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP's CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x).

RESET

I/A

Processor Reset. Resets the ADSP-21160N to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.

TCK

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

TMS

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k

internal pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 k

internal pull-up resistor.

TDO

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Test Reset (JTAG). Resets the test state machine.

TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21160N.

TRST has a

20 k

internal pull-up resistor.

EMU

O (O/D)

Emulation Status. Must be connected to the ADSP-21160N emulator target board
connector only. EMU has a 50 k

internal pull-up resistor.

CIF

O/T

Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master.

CIF has a

20k

internal pull-up resistor that is enabled on the ADSP-21160N with ID20 = 00x.

DDINT

Core Power Supply. Nominally 1.9 V dc and supplies the DSP's core processor
(40 pins).

DDEXT

I/O Power Supply. Nominally 3.3 V dc (43 pins).

Analog Power Supply. Nominally 1.9 V dc and supplies the DSP's internal PLL (clock
generator). This pin has the same specifications as V

DDINT

, except that added filtering

circuitry is required.

For more information, see Power Supplies on page 6.

AGND

Analog Power Supply Return.

GND

Power Supply Return. (82 pins)

Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).

Table 3. Boot Mode Selection

EBOOT

LBOOT

BMS

Booting Mode

Output

EPROM (Connect

BMS to EPROM chip select.)

1 (Input)

Host Processor

1 (Input)

Link Port

0 (Input)

No Booting. Processor executes from external memory.

0 (Input)

Reserved

x (Input)

Reserved

Table 2. Pin Function Descriptions (Continued)

Pin

Type

Function

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

ADSP-21160N SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Signal

Parameter

C Grade

K Grade

Unit

Min Max

DDINT

Internal (Core) Supply Voltage

1.8

2.0

1.8

2.0

Analog (PLL) Supply Voltage

1.8

2.0

1.8

2.0

DDEXT

External (I/O) Supply Voltage

3.13

3.47

3.13

3.47

CASE

Case Operating Temperature

+ 100

ºC

IH1

High Level Input Voltage

, @ V

DDEXT

= Max

2.2

DDEXT

+ 0.5

2.2

DDEXT

+ 0.5

IH2

High Level Input Voltage

, @ V

DDEXT

= Max

2.3

DDEXT

+ 0.5

2.3

DDEXT

+ 0.5

Low Level Input Voltage

3,4

, @ V

DDEXT

= Min

0.5

0.8

0.5

0.8

Specifications subject to change without notice.

See

Environmental Conditions on page 48

for information on thermal specifications.

Applies to input and bidirectional pins: DATA630, ADDR310,

RDx, WRx, ACK, SBTS, IRQ20, FLAG30, HBG, CS, DMAR1, DMAR2, BR61,

ID20, RPBA,

PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT30, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1.

Applies to input pins: CLKIN,

RESET, TRST.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

C and K Grades

Unit

Min

Max

High Level Output Voltage

@ V

DDEXT

= Min, I

= 2.0 mA

2.4

Low Level Output Voltage

@ V

DDEXT

= Min, I

= 4.0 mA

0.4

High Level Input Current

4,5,6

@ V

DDEXT

= Max, V

= V

Max

µA

Low Level Input Current

@ V

DDEXT

= Max, V

= 0 V

µA

ILPU1

Low Level Input Current Pull-Up1

@ V

DDEXT

= Max, V

= 0 V

250

µA

ILPU2

Low Level Input Current Pull-Up2

@ V

DDEXT

= Max, V

= 0 V

500

µA

OZH

Three-State Leakage Current

7,8,9,10

@ V

DDEXT

= Max, V

= V

Max

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= Max, V

= 0 V

µA

OZHPD

Three-State Leakage Current
Pull-Down

@ V

DDEXT

= Max, V

= V

Max

250

µA

OZLPU1

Three-State Leakage Current
Pull-Up1

@ V

DDEXT

= Max, V

= 0 V

250

µA

OZLPU2

Three-State Leakage Current
Pull-Up2

@ V

DDEXT

= Max, V

= 0 V

500

µA

OZHA

Three-State Leakage Current

@ V

DDEXT

= Max, V

= V

Max

µA

OZLA

Three-State Leakage Current

@ V

DDEXT

= Max, V

= 0 V

DD-INPEAK

Supply Current (Internal)

CCLK

= 10.5 ns, V

DDINT

= Max

1400

DD-INHIGH

Supply Current (Internal)

CCLK

= 10.5 ns, V

DDINT

= Max

875

DD-INLOW

Supply Current (Internal)

CCLK

= 10.5 ns, V

DDINT

= Max

625

DD-IDLE

Supply Current (Idle)

CCLK

= 10.5 ns, V

DDINT

= Max

400

Supply Current (Analog)

@AV

= Max

Input Capacitance

17,18

= 1 MHz, T

CASE

= 25°C,

= 2.5 V

4.7

Specifications subject to change without notice.

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Applies to output and bidirectional pins: DATA630, ADDR310,

MS30, RDx, WRx, PAGE, CLKOUT, ACK, FLAG30, TIMEXP, HBG, REDY,

DMAG1, DMAG2, BR61, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT30, LxCLK,
LxACK,

BMS, TDO, EMU.

See

Output Drive Currents on page 46

for typical drive current capabilities.

Applies to input pins:

SBTS, IRQ20, HBR, CS, ID20, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.

Applies to input pins with internal pull-ups: DR0, DR1.

Applies to input pins with internal pull-ups:

DMARx, TMS, TDI, TRST.

Applies to three-statable pins: DATA630, ADDR310, PAGE, CLKOUT, ACK, FLAG30, REDY,

HBG, BMS, BR61, TFSx, RFSx, TDO.

Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.

Applies to three-statable pins with internal pull-ups:

MS30, RDx, WRx, DMAGx, PA, CIF.

Applies to three-statable pins with internal pull-downs: LxDAT70, LxCLK, LxACK.

Applies to ACK pulled up internally with 2 k

during reset or ID20 = 00x.

The test program used to measure I

DD-INPEAK

represents worst case processor operation and is not sustainable under normal application conditions. Actual

internal power measurements made using typical applications are less than specified.

For more information, see Power Dissipation on page 46.

DDINHIGH

is a composite average based on a range of high activity code.

For more information, see Power Dissipation on page 46.

DDINLOW

is a composite average based on a range of low activity code.

For more information, see Power Dissipation on page 46.

Idle denotes ADSP-21160N state during execution of IDLE instruction.

For more information, see Power Dissipation on page 46.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

Internal (Core) Supply Voltage (V

DDINT

)

. . 0.3 V to +2.3 V

Analog (PLL) Supply Voltage (A

VDD

) . . . . . 0.3 V to +2.3 V

External (I/O) Supply Voltage (V

DDEXT

) . . . . 0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . 0.5 V to V

DDEXT

+ 0.5 V

Output Voltage Swing . . . . . . . . . . . 0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature under Bias . . . . . . . . . . . . . . . 130ºC

Storage Temperature Range. . . . . . . . . . . 65ºC to +150ºC

Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160N features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Timing Specifications

The ADSP-21160N's internal clock switches at higher fre-
quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP's
internal clock (the clock source for the external port logic
and I/O pads).

The ADSP-21160N's internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP's
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG30 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre-
quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD10 for the link ports).

Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:

CCLK

= (t

) / CR

LCLK

= (t

CCLK

) LR

SCLK

= (t

CCLK

) SR

Where:

LCLK = Link Port Clock

SCLK = Serial Port Clock

= CLKIN Clock Period

CCLK

= (Processor) Core Clock Period

LCLK

= Link Port Clock Period

SCLK

= Serial Port Clock Period

CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG30 at reset)

LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)

SR = Serial Port/Core Clock Ratio (wide range,
determined by CLKDIV)

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning-
ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con-
sequently, it is not meaningful to add parameters to derive
longer times.

See

Figure 34

under Test Conditions for voltage reference

levels.

Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris-
tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris-
tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.

During processor reset (RESET pin low) or software reset
(SRST bit in SYSCON register = 1), de-assertion (MS3-0,
HBG, DMAGx, RDx, WRx, CIF, PAGE, BRST) and
three-state (FLAG3-0, LxCLK, LxACK, LxDAT7-0,
ACK, REDY, PA, TFSx, RFSx, TCLKx, RCLKx, DTx,
BMS, TDO, EMU, DATA) timings differ. These occur
asynchronously to CLKIN, and may not meet the specifi-
cations published in the Timing Requirements and
Switching Characteristics tables. The maximum delay for
de-assertion and three-state is one t

from RESET pin

assertion low or setting the SRST bit in SYSCON. During
reset the DSP will not respond to

SBTS, HBR and MMS

accesses.

HBR asserted before reset will be recognized, but

HBG will not be returned by the DSP until after reset is

de-asserted and the DSP has completed bus
synchronization.

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Power-up Sequencing

During the power up sequence of the DSP, differences in
the ramp up rates and activation time between the two power
supplies can cause current to flow in the I/O ESD protection
circuitry. To prevent this damage to the ESD diode protec-
tion circuitry, Analog Devices, Inc. recommends including
a bootstrap Schottky diode (see

Figure 11 on page 18

. The

bootstrap Schottky diode connected between the 1.9V and

3.3V power supplies protects the ADSP-21160N from
partially powering the 3.3V supply. Including a Schottky
diode will shorten the delay between the supply ramps and
thus prevent damage to the ESD diode protection circuitry.
With this technique, if the 1.9V rail rises ahead of the 3.3V
rail, the Schottky diode pulls the 3.3V rail along with the
1.9V rail.

Table 4. Power-up Sequencing

Parameter

Min

Max

Unit

Timing Requirements:
t

RSTVDD

RESET low before V

DDINT

DDEXT

IVDDEVDD

DDINT

on before V

DDEXT

-50

200

CLKVDD

CLKIN running after valid V

DDINT

DDEXT

200

CLKRST

CLKIN valid before

RESET de-asserted

µs

PLLRST

PLL control setup before

RESET de-asserted

TBD

Switching Characteristics:
t

CORERST

DSP core reset de-asserted after RESET de-asserted

4096*t

4,5

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.9 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds

of milliseconds, depending on the design of the power supply subsystem.

CLKIN should be driven coincident with power-up to avoid an undefined state in internal gates, which may cause excess current flow.

Assumes a stable CLKIN signal after meeting worst case start up timing of oscillators. Refer to your oscillator manufacturer's data sheet for start up time.

Based on CLKIN cycles.

CORERST is an internal signal only. The 4096 cycle count is dependent on t

SRST

specification. If setup time is not met, one additional CLKIN cycle may

be added to the core reset time, resulting in 4097 cycles maximum.

Figure 10. Power-up Sequencing

CLKIN

RESET

RSTVDD

VDDEXT

VDDINT

IVDDEVDD

CLKVDD

CLKRST

PLLRST

CORERST

CLK_CFG3-0

CORERST

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Flags

Table 9. Flags

Parameter

Min

Max

Unit

Timing Requirements:
t

SFI

FLAG30 IN Setup Before CLKIN High

Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N + 2.

HFI

FLAG30 IN Hold After CLKIN High

DWRFI

FLAG30 IN Delay After

RDx/WRx Low

HFIWR

FLAG30 IN Hold After

RDx/WRx Deasserted

Switching Characteristics:

DFO

FLAG30 OUT Delay After CLKIN High

HFO

FLAG30 OUT Hold After CLKIN High

DFOE

CLKIN High to FLAG30 OUT Enable

DFOD

CLKIN High to FLAG30 OUT Disable

CCLK

+ 5

Figure 16. Flags

CLKIN

FLAG30

OUT

FLAG OUTPUT

CLKIN

RDX

FLAG INPUT

FLAG30

DFO

HFO

DFO

DFOD

DFOE

SFI

HFI

HFIWR

DWRFI

WRX

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Memory Read--Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-
chronous access mode. Note that timing for ACK, DATA,

RDx, WRx, and DMAG strobe timing parameters only applies

to asynchronous access mode.

Table 10. Memory Read--Bus Master

Parameter

Min

Max

Unit

Timing Requirements:
t

DAD

Address,

CIF, Selects Delay to Data

Valid

1,2

Data Delay/Setup: User must meet t

DAD

, t

DRLD

, or t

SDS.

The falling edge of

MSx, BMS is referenced.

0.25t

CCLK

11 + W

DRLD

RDx Low to Data Valid

1,3

Note that timing for ACK, DATA,

RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

0.5t

CCLK

+ W

HDA

Data Hold from Address, Selects

Data Hold: User must meet t

HDA

or t

HDRH

in asynchronous access mode. See

Example System Hold Time Calculation on page 47

for the calculation of

hold times given capacitive and dc loads.

SDS

Data Setup to

RDx High

HDRH

Data Hold from

RDx High

3,4

DAAK

ACK Delay from Address, Selects

2,5

ACK Delay/Setup: User must meet t

DAAK

, t

DSAK

, or t

SAKC

for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

0.5t

CCLK

12 + W

DSAK

ACK Delay from

RDx Low

3,5

0.75t

CCLK

11 + W

SAKC

ACK Setup to CLKIN

3,5

0.5t

CCLK

+ 3

HAKC

ACK Hold After CLKIN

Switching Characteristics:

DRHA

Address,

CIF, Selects Hold After RDx

High

0.25t

CCLK

1 + H

DARL

Address,

CIF, Selects to RDx Low

0.25t

CCLK

RDx Pulse width

0.5t

CCLK

1 + W

RWR

RDx High to WRx, RDx, DMAGx Low

0.5t

CCLK

1 + HI

W = (number of wait states specified in WAIT register) t

HI = t

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t

(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Memory Write--Bus Master

RDx, WRx, and DMAG strobe timing parameters only applies

to asynchronous access mode.

Table 11. Memory Write--Bus Master

Parameter

Min

Max

Unit

Timing Requirements:
t

DAAK

ACK Delay from Address, Selects

1,2

ACK Delay/Setup: User must meet t

DAAK

or t

DSAK

or t

SAKC

for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

The falling edge of

MSx, BMS is referenced.

0.5t

CCLK

12 + W

DSAK

ACK Delay from

WRx Low

1,3

Note that timing for ACK, DATA,

RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

0.75t

CCLK

11 + W

SAKC

ACK Setup to CLKIN

1,3

0.5t

CCLK

+ 3

HAKC

ACK Hold After CLKIN

1,3

Switching Characteristics:

DAWH

Address,

CIF, Selects to WRx

Deasserted

2,3

0.25t

CCLK

3 + W

DAWL

Address,

CIF, Selects to WRx Low

0.25t

CCLK

WRx Pulse width

0.5t

CCLK

1 + W

DDWH

Data Setup before

WRx High

C K

0.5t

CCLK

1 + W

DWHA

Address Hold after

WRx Deasserted

0.25t

CCLK

1 + H

DWHD

Data Hold after

WRx Deasserted

0.25t

CCLK

1 + H

DATRWH

Data Disable after

WRx Deasserted

3,4

See

Example System Hold Time Calculation on page 47

for calculation of hold times given capacitive and dc loads.

0.25t

CCLK

2 + H

0.25t

CCLK

+ 2 + H

WWR

WRx High to WRx, RDx, DMAGx Low

0.5t

CCLK

1 + HI

DDWR

Data Disable before

WRx or RDx Low

0.25t

CCLK

1 + I

WDE

WRx Low to Data Enabled

0.25t

CCLK

W = (number of wait states specified in WAIT register) × t

H = t

(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t

(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

Figure 18. Memory Write--Bus Master

DATRWH

RDx

ACK

DATA

WRx

ADDRESS

MSx

BMS

CIF

DAWL

DAAK

WWR

WDE

DDWR

DWHA

DAWH

DSAK

DDWH

DWHD

SAKC

HAKC

CLKIN

DMAG

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Synchronous Read/Write--Bus Master

Use these specifications for interfacing to external memory systems that require CLKIN--relative timing or for accessing
a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see

Memory Read--Bus Master on page 24

and

Memory

Write--Bus Master on page 26

). When accessing a slave ADSP-21160N, these switching characteristics must meet the

slave's timing requirements for synchronous read/writes (see

Synchronous Read/Write--Bus Slave on page 29

). The slave

ADSP-21160N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.

Table 12. Synchronous Read/Write--Bus Master

Parameter

Min

Max

Unit

Timing Requirements:
t

SSDATI

Data Setup Before CLKIN

Note that timing for ACK, DATA,

RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.

5.5

HSDATI

Data Hold After CLKIN

SACKC

ACK Setup Before CLKIN

0.5t

CCLK

+ 3

HACKC

ACK Hold After CLKIN

Switching Characteristics:

DADDO

Address,

MSx, BMS, BRST, CIF Delay After CLKIN

HADDO

Address,

MSx, BMS, BRST, CIF Hold After CLKIN

1.5

DPGO

PAGE Delay After CLKIN

1.5

DRDO

RDx High Delay After CLKIN

0.25t

CCLK

0.25t

CCLK

+ 9

DWRO

WRx High Delay After CLKIN

0.25t

CCLK

0.25t

CCLK

+ 9

DRWL

RDx/WRx Low Delay After CLKIN

0.25t

CCLK

0.25t

CCLK

+ 9

DDATO

Data Delay After CLKIN

0.25t

CCLK

+ 9

HDATO

Data Hold After CLKIN

1.5

DACKMO

ACK Delay After CLKIN

Applies to broadcast write, master precharge of ACK.

ACKMTR

ACK Disable Before CLKIN

DCKOO

CLKOUT Delay After CLKIN

CKOP

CLKOUT Period

+ 1

Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter

in the ADSP-2116x SHARC DSP Hardware Reference.

CKWH

CLKOUT Width High

/2 2

/2 + 2

CKWL

CLKOUT Width Low

/2 2

/2 + 2

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Synchronous Read/Write--Bus Slave

Use these specifications for ADSP-21160N bus master accesses of a slave's IOP registers or internal memory (in multipro-
cessor memory space). The bus master must meet these (bus slave) timing requirements.

Table 13. Synchronous Read/Write--Bus Slave

Parameter

Min

Max

Unit

Timing Requirements:
t

SADDI

Address, BRST Setup Before CLKIN

HADDI

Address, BRST Hold After CLKIN

SRWI

RDx/WRx Setup Before CLKIN

HRWI

RDx/WRx Hold After CLKIN

SSDATI

Data Setup Before CLKIN

5.5

HSDATI

Data Hold After CLKIN

Switching Characteristics:

DDATO

Data Delay After CLKIN

0.25 t

CCLK

+ 9

HDATO

Data Hold After CLKIN

1.5

DACKC

ACK Delay After CLKIN

HACKO

ACK Hold After CLKIN

1.5

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (

BRx) or a host processor

(

HBR, HBG).

Table 14. Multiprocessor Bus Request and Host Bus Request

Parameter

Min

Max

Unit

Timing Requirements:
t

HBGRCSV

HBG Low to RDx/WRx/CS Valid

6.5 + t

+ t

CCLK

12.5CR

SHBRI

HBR Setup Before CLKIN

Only required for recognition in the current cycle.

HHBRI

HBR Hold After CLKIN

SHBGI

HBG Setup Before CLKIN

HHBGI

HBG Hold After CLKIN High

SBRI

BRx, PA Setup Before CLKIN

HBRI

BRx, PA Hold After CLKIN High

SRPBAI

RPBA Setup Before CLKIN

HRPBAI

RPBA Hold After CLKIN

Switching Characteristics:

DHBGO

HBG Delay After CLKIN

HHBGO

HBG Hold After CLKIN

DBRO

BRx Delay After CLKIN

HBRO

BRx Hold After CLKIN

1.5

DPASO

PA Delay After CLKIN, Slave

TRPAS

PA Disable After CLKIN, Slave

1.5

DPAMO

PA Delay After CLKIN, Master

0.25t

CCL K

+ 9

PATR

PA Disable Before CLKIN, Master

0.25t

CCLK

DRDYCS

REDY (O/D) or (A/D) Low from

CS and HBR Low

(O/D) = open drain, (A/D) = active drive.

0.5t

TRDYHG

REDY (O/D) Disable or REDY (A/D) High from

HBG

+ 20

ARDYTR

REDY (A/D) Disable from CS or HBR High

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Asynchronous Read/Write--Host to ADSP-21160N

Use these specifications (

Table 15

and

Table 16

) for asynchronous host processor accesses of an ADSP-21160N, after the

host has asserted

CS and HBR (low). After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx

pins to access the ADSP-21160N's internal memory or IOP registers.

HBR and HBG are assumed low for this timing

Table 15. Read Cycle

Parameter

Min

Max

Unit

Timing Requirements:
t

SADRDL

Address Setup/

CS Low Before RDx Low

HADRDH

Address Hold/

CS Hold Low After RDx

WRWH

RDx/WRx High Width

DRDHRDY

RDx High Delay After REDY (O/D) Disable

DRDHRDY

RDx High Delay After REDY (A/D) Disable

Switching Characteristics:

SDATRDY

Data Valid Before REDY Disable from Low

DRDYRDL

REDY (O/D) or (A/D) Low Delay After

RDx Low

RDYPRD

REDY (O/D) or (A/D) Low Pulsewidth for Read

- 3

HDARWH

Data Disable After RDx High

Figure 22. Read Cycle (Asynchronous Read--Host to ADSP-21160N)

READ CYCLE

REDY (O/ D)

RDx

ADDRESS/

D ATA (OUT)

REDY (A/D)

S AD R D L

D RD YRD L

WR WH

H AD R D H

H D A R WH

RD Y PR D

D R D HR D Y

SD A TR DY

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Table 16. Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:
t

SCSWRL

CS Low Setup Before WRx Low

HCSWRH

CS Low Hold After WRx High

SADWRH

Address Setup Before

WRx High

HADWRH

Address Hold After

WRx High

WWRL

WRx Low Width

WRWH

RDx/WRx High Width

DWRHRDY

WRx High Delay After REDY (O/D) or (A/D) Disable

SDATWH

Data Setup Before

WRx High

HDATWH

Data Hold After

WRx High

Switching Characteristics:

DRDYWRL

REDY (O/D) or (A/D) Low Delay After

WRx/CS Low

RDYPWR

REDY (O/D) or (A/D) Low Pulsewidth for Write

5.75 + 0.5t

CCLK

Figure 23. Write Cycle (Asynchronous Write--Host to ADSP-21160N)

O/D = O PEN DRAIN, A/D = ACT IVE

DRI VE

REDY (O /D)

WRx

WRITE CY CLE

DATA (I N)

ADDRESS

REDY (A/D)

SD A TW H

H D A TW H

WWR L

D R D YW RL

WR WH

H AD W RH

R D YP WR

D WR H R DY

SA D WR H

S C SW R L

T HC S WR H

PRELIMINARY TECHNICAL DATA

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

Three-State Timing--Bus Master and Bus Slave

These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to
CLKIN and the

SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC)

as well as the

SBTS pin.

Table 17. Three-State Timing--Bus Slave,

HBR, SBTS

Parameter

Min

Max

Unit

Timing Requirements:
t

STSCK

SBTS Setup Before CLKIN

HTSCK

SBTS

Hold After CLKIN

Switching Characteristics:

MIENA

Address/Select Enable After CLKIN

1.5

MIENS

Strobes Enable After CLKIN

Strobes =

RDx, WRx, DMAGx.

1.5

MIENHG

HBG Enable After CLKIN

1.5

MITRA

Address/Select Disable After CLKIN

1.5

MITRS

Strobes Disable After CLKIN

1,2

If access aborted by

SBTS, then strobes disable before CLKIN [0.25t

CCLK

+ 1.5 (min.), 0.25t

CCLK

+ 5 (max.)]

0.25t

CCLK

0.25t

CCLK

MITRHG

HBG Disable After CLKIN

3.5

DATEN

Data Enable After CLKIN

In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

0.25t

CCLK

+ 1

0.25t

CCLK

+ 7

DATTR

Data Disable After CLKIN

1.5

ACKEN

ACK Enable After CLKIN

1.5

ACKTR

ACK Disable After CLKIN

1.5

CDCEN

CLKOUT Enable After CLKIN

1.5

CDCTR

CLKOUT Disable After CLKIN

CCLK

+ 1

ATRHBG

Address,

MSx Disable Before HBG Low

1.5t

+ 1.5

1.5t

+ 5

STRHBG

RDx, WRx, DMAGx Disable Before HBG Low

+ 0.25t

CCLK

+ 1.5

+ 0.25t

CCLK

+ 5

PTRHBG

Page Disable Before

HBG Low

+ 1.5

+ 5

BTRHBG

BMS Disable Before HBG Low

0.5t

+ 1.5

0.5t

+ 1.5

MENHBG

Memory Interface Enable After HBG High

Memory Interface = Address,

RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).

+ 5

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

DMA Handshake

These specifications describe the three DMA handshake modes. In all three modes

DMAR is used to initiate transfers. For

handshake mode,

DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer

is controlled by the ADDR310,

RDx, WRx, PAGE, MS30, ACK, and DMAG signals. For Paced Master mode, the data

transfer is controlled by ADDR310,

RDx, WRx, MS30, and ACK (not DMAG). For Paced Master mode, the Memory

Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR310,

RDx, WRx, MS30, PAGE, DATA630, and ACK also apply.

Table 18. DMA Handshake

Parameter

Min

Max

Unit

Timing Requirements:
t

SDRC

DMARx Setup Before CLKIN

Only required for recognition in the current cycle.

WDR

DMARx Width Low (Nonsynchronous)

Maximum throughput using

DMARx/DMAGx handshaking equals t

WDR

+ t

DMARH

= (0.5t

CCLK

+ 1) + (0.5t

CCLK

+ 1) = 12.5 ns (80 MHz). This throughput

limit applies to non-synchronous access mode only.

0.5t

CCLK

+ 1

SDATDGL

Data Setup After

DMAGx Low

SDATDGL

is the data setup requirement if

DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of

the write, the data can be driven t

DATDRH

after

DMARx is brought high.

0.5t

CCLK

HDATIDG

Data Hold After

DMAGx High

DATDRH

Data Valid After

DMARx High

+ 3

DMARLL

DMARx Low Edge to Low Edge

Use t

DMARLL

DMARx transitions synchronous with CLKIN. Otherwise, use t

WDR

and t

DMARH

DMARx Width High

0.5t

CCLK

+ 1

Switching Characteristics:

DDGL

DMAGx Low Delay After CLKIN

0.25t

CCLK

+ 1

0.25t

CCLK

+ 9

WDGH

DMAGx High Width

0.5t

CCLK

1 + HI

WDGL

DMAGx Low Width

0.5t

CCLK

HDGC

DMAGx High Delay After CLKIN

0.25t

CCLK

+ 1.5

0.25t

CCLK

+ 9

VDATDGH

Data Valid Before

DMAGx High

VDATDGH

is valid if

DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then

VDATDGH

= t

.25t

CCLK

8 + (n × t

) where n equals the number of extra cycles that the access is prolonged.

0.25t

CCLK

0.25t

CCLK

+ 5

DATRDGH

Data Disable After

DMAGx High

See

Example System Hold Time Calculation on page 47

for calculation of hold times given capacitive and dc loads.

0.25t

CCLK

0.25t

CCLK

+ 1.5

DGWRL

WRx Low Before DMAGx Low

1.5

DGWRH

DMAGx Low Before WRx High

0.5t

CCLK

2 + W

DGWRR

WRx High Before DMAGx High

This parameter applies for synchronous access mode only.

1.5

DGRDL

RDx Low Before DMAGx Low

1.5

DRDGH

RDx Low Before DMAGx High

0.5t

CCLK

2 + W

DGRDR

RDx High Before DMAGx High

1.5

DGWR

DMAGx High to WRx, RDx, DMAGx
Low

0.5t

CCLK

2 + HI

DADGH

Address/Select Valid to

DMAGx High

DDGHA

Address/Select Hold after

DMAGx High

W = (number of wait states specified in WAIT register) t

HI = t

(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Figure 25. DMA Handshake Timing

CLKIN

SDRC

DMARx

DATA

RDx

WRx

WDR

SDRC

DMARH

DMARLL

HDGC

WDGH

DDGL

DMAGx

VDATDGH

DATDRH

DATRDGH

HDATIDG

DGWRL

DGWRH

DGWRR

DGRDL

DRDGH

DGRDR

SDATDGL

* MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR310, RDX, WRX, MS30 AND ACK ALSO APPLY HERE.

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

TRANSFERS BETWEEN ADSP-2116X

INTERNAL MEMORY AND EXTERNAL DEVICE

TRANSFERS BETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

DDGHA

ADDR

MSX

DADGH

WDGL

(FROM EXTERNAL DRIVE TO ADSP-2116X)

(FROM ADSP-2116X TO EXTERNAL DRIVE)

PRELIMINARY TECHNICAL DATA

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ADSP-21160N

April 2002

Link Ports

Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximin allowable skew
that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA, relative to LCLK (setup skew = t

LCLKTWH

minimum t

DLDCH

SLDCL

). Hold skew is the maximum

delay that can be introduced in LCLK, relative to LDATA (hold skew = t

LCLKTWL

minimum + t

HLDCH

HLDCL

).Calculations

made directly from speed specifications result in unrealistically small skew times, because they include multiple tester
guardbands.

Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port.

Table 19. Link Ports--Receive

Parameter

Min

Max

Unit

Timing Requirements:
t

SLDCL

Data Setup Before LCLK Low

2.5

HLDCL

Data Hold After LCLK Low

2.5

LCLKIW

LCLK Period

LCLK

LCLKRWL

LCLK Width Low

LCLKRWH

LCLK Width High

Switching Characteristics:

DLALC

LACK Low Delay After LCLK High

LACK goes low with t

DLALC

relative to rise of LCLK after first nibble, but doesn't go low if the receiver's link buffer is not about to fill.

Figure 26. Link Ports--Receive

LCLK

LDAT(7:0)

LACK (OUT)

RECEIVE

SLDCL

HLDCL

LCLKRWH

DLALC

LCLKRWL

LCLKIW

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Table 20. Link Ports--Transmit

Parameter

Min

Max

Unit

Timing Requirements:
t

SLACH

LACK Setup Before LCLK High

HLACH

LACK Hold After LCLK High

Switching Characteristics:

DLDCH

Data Delay After LCLK High

6.0

HLDCH

Data Hold After LCLK High

LCLKTWL

LCLK Width Low

0.5t

LCLK

0.5t

LCLK

+ .5

LCLKTWH

LCLK Width High

0.5t

LCLK

0.5t

LCLK

+ .5

DLACLK

LCLK Low Delay After LACK High

0.5t

LCLK

+ 5

LCLK

+ 11

Figure 27. Link Ports--Transmit

LCLK

LDAT(7:0)

LACK (IN)

THE

SLACH

REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

TRANSMIT

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

LCLK INACTIVE

(HIGH)

OUT

DLDCH

HLDCH

LCLKTWH

LCLKTWL

SLACH

HLACH

DLACLK

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Serial Ports

To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

Table 21. Serial Ports--External Clock

Parameter

Min

Max

Unit

Timing Requirements:
t

SFSE

TFS/RFS Setup Before TCLK/RCLK

Referenced to sample edge.

3.5

HFSE

TFS/RFS Hold After TCLK/RCLK

1,2

RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

SDRE

Receive Data Setup Before RCLK

1.5

HDRE

Receive Data Hold After RCLK

SCLKW

TCLK/RCLK Width

SCLK

TCLK/RCLK Period

CCLK

Table 22. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Timing Requirements:
t

SFSI

TFS Setup Before TCLK

; RFS Setup Before RCLK

Referenced to sample edge.

HFSI

TFS/RFS Hold After TCLK/RCLK

1,2

RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

CCLK

/2 + 1

SDRI

Receive Data Setup Before RCLK

6.5

HDRI

Receive Data Hold After RCLK

Table 23. Serial Ports--External or Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:
t

DFSE

RFS Delay After RCLK (Internally Generated RFS)

Referenced to drive edge.

HOFSE

RFS Hold After RCLK (Internally Generated RFS)

Table 24. Serial Ports--External Clock

Parameter

Min

Max

Unit

Switching Characteristics:
t

DFSE

TFS Delay After TCLK (Internally Generated TFS)

Referenced to drive edge.

HOFSE

TFS Hold After TCLK (Internally Generated TFS)

DDTE

Transmit Data Delay After TCLK

HDTE

Transmit Data Hold After TCLK

Table 25. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics:
t

DFSI

TFS Delay After TCLK (Internally Generated TFS)

4.5

HOFSI

TFS Hold After TCLK (Internally Generated TFS)

1.5

PRELIMINARY TECHNICAL DATA

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ADSP-21160N

April 2002

Figure 28. Serial Ports

DRIVE EDGE

DRIVE

EDGE

DRIVE

EDGE

TCLK /

RCLK

TCLK

(INT)

TCLK /

RCLK

TCLK
(EXT)

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

DATA RECEIVE-- INTERNAL CLOCK

DATA RECEIVE-- EXTERNAL CLOCK

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

DATA TRANSMIT-- INTERNAL CLOCK

DATA TRANSMIT-- EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTTE

DDTEN

DDTTI

DDTIN

SDRI

HDRI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

SDRE

HDRE

SFSE

HFSE

DFSE

SCLKW

HOFSE

DDTI

HDTI

SFSI

HFSI

SCLKIW

DFSI

HOFSI

DDTE

HDTE

SFSE

HFSE

DFSE

SCLKW

HOFSE

PRELIMINARY TECHNICAL DATA

REV. PrB

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ADSP-21160N

April 2002

Table 27. Serial Ports--External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics:
t

DDTLFSE

Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 0

MCE = 1, TFS enable and TFS valid follow t

DDTLFSE

and t

DDTENFS

Data Enable from late FS or MCE = 1, MFD = 0

1.0

Figure 29. External Late Frame Sync

(SEE NOTE 2)

DRIVE

SAMPLE

DRIVE

TCLK

TFS

DRIVE

SAMPLE

DRIVE

LATE EXTERNAL TFS

EXTERNAL RFS WITH MCE = 1, MFD = 0

1ST BIT

2ND BIT

RCLK

RFS

1ST BIT

2ND BIT

(SEE NOTE 2)

HOFSE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

HOFSE/I

SFSE/I

DDTE/I

TDDTENFS

DDTLFSE

HDTE/I

REV. PrB

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PRELIMINARY TECHNICAL DATA

JTAG Test Access Port and Emulation

Table 28. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements:
t

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK Low

HSYS

System Inputs Hold After TCK Low

TRSTW

TRST Pulsewidth

4 t

Switching Characteristics:

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

System Inputs = DATA630, ADDR310,

RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR61, ID20, RPBA, IRQ20, FLAG30,

PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT70, LxCLK, LxACK, EBOOT, LBOOT, BMS,
CLKIN,

RESET.

System Outputs = DATA630, ADDR310,

MS30, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR61, PA, BRST, CIF,

FLAG30, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT70, LxCLK, LxACK,

BMS.

Figure 30. IEEE 11499.1 JTAG Test Access Port

TCK

TMS
TDI

TDO

SYSTEM
INPUTS

SYSTEM
OUTPUTS

STAP

TCK

HTAP

DTDO

SSYS

HSYS

DSYS

REV. PrB

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ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Output Drive Currents

Figure 31

shows typical IV characteristics for the output

drivers of the ADSP-21160N. The curves represent the
current drive capability of the output drivers as a function
of output voltage.

Power Dissipation

Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers.

Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using
the current specifications (I

DDINPEAK

, I

DDINHIGH

, I

DDINLOW

, I

DDIDLE

)

from

Electrical Characteristics on page 13

and the cur-

rent-versus-operation information in

Table 29

, engineers

can estimate the ADSP-21160N's internal power supply
(V

DDINT

) input current for a specific application, according

to the following formula:

The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on:

the number of output pins that switch during each
cycle (O)

the maximum frequency at which they can switch (f)

their load capacitance (C)

their voltage swing (VDD)

and is calculated by:

EXT

= O × C × V

× f

The load capacitance should include the processor's
package capacitance (C

). The switching frequency

includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2 t

). The write strobe can switch every cycle at a

frequency of 1/t

. Select pins switch at 1/(2 t

), but selects

can switch on each cycle.

Figure 31. ADSP-21160N Typical Drive Currents

SOURCE(V

DDEXT

) VOLTAGEV

120

3.5

0.5

1.5

2.5

(
V

)

100

80

60

40

20

100

120

DDEXT

=3.47V, 40°C

DDEXT

= 3.3V, 25°C

DDEXT

= 3.13V, 100°C

DDEXT

= 3.47V, 40°C

DDEXT

= 3.3V, 25°C

DDEXT

= 3.13V, 100°C

% Peak I

DDINPEAK

% High I

DDINHIGH

% Low I

DDINLOW

+ % Idle I

DDIDLE

DDINT

--------------------------------------------------

Table 29. ADSP-21160N Operation Types vs. Input Current

Operation

Peak Activity

High Activity

Low Activity

Instruction Type

Multifunction

Single Function

Instruction Fetch

Cache

Internal Memory

Core Memory Access

2 per t

cycle

(DM 64 and PM 64)

1 per t

cycle

(DM 64)

None

Internal Memory DMA

1 per 2 t

CCLK

cycles

1 per 2 t

CCLK

cycles

None

External Memory DMA

1 per external port cycle ( 64)

None

Data bit pattern for core
memory access and DMA

Worst case

Random

N/A

Peak Activity = I

DDINPEAK

, High Activity = I

DDINHIGH

, and Low Activity = I

DDINLOW

. The state of the PEYEN bit (SIMD versus SISD mode) does not influence

these calculations.

These assume a 2:1 core clock ratio. For more information on ratios and clocks (t

and t

CCLK

), see the timing ratio definitions

on page 16

REV. PrB

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ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

Example: Estimate P

EXT

with the following assumptions:

A system with one bank of external data memory--asyn-
chronous RAM (64-bit)

Four 64K × 16 RAM chips are used, each with a load of
10 pF

External data memory writes occur every other cycle, a
rate of 1/(2 t

), with 50% of the pins switching

The bus cycle time is 47.5 MHz (t

= 21 ns).

The P

EXT

equation is calculated for each class of pins that

can drive:

A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:

TOTAL

= P

EXT

+ P

INT

+ P

PLL

Where:

EXT

is from

Table 30

INT

is I

DDINT

× 1.9 V, using the calculation I

DDINT

listed in

Power Dissipation on page 46

PLL

is AI

× 1.9 V, using the value for AI

listed in

ABSOLUTE MAXIMUM RATINGS on page 15

Note that the conditions causing a worst-case P

EXT

are

different from those causing a worst-case P

INT

. Maximum

INT

cannot occur while 100% of the output pins are

switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.

Test Conditions

The test conditions for timing parameters appearing in

ADSP-21160N specifications on page 13

include output

disable time, output enable time, and capacitive loading.

Output Disable Time

Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by

V is dependent on the

capacitive load, C

and the load current, I

. This decay time

can be approximated by the following equation:

DECAY

= (C

V)/I

The output disable time t

DIS

is the difference between

MEASURED

and t

DECAY

as shown in

Figure 32

. The time t

MEASURED

is the interval from when the reference signal switches to
when the output voltage decays

V from the measured

output high or output low voltage. t

DECAY

is calculated with

test loads C

and I

, and with

V equal to 0.5 V.

Output Enable Time

Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t

ENA

is the interval from

when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(

Figure 32

). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to
start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular
system, first calculate t

DECAY

using the equation given above.

Choose V to be the difference between the
ADSP-21160N's output voltage and the input threshold for
the device requiring the hold time. A typical V will be
0.4 V. C

is the total bus capacitance (per data line), and I

is the total leakage or three-state current (per data line). The
hold time will be t

DECAY

plus the minimum disable time (i.e.,

DATRWH

for the write cycle).

Table 30. External Power Calculations (3.3 V Device)

Pin Type

# of Pins

% Switching

× C

× f

× VDD

= P

EXT

Address

× 44.7 pF

× 24 MHz

× 10.9 V

= 0.088 W

MS0

× 44.7 pF

× 24 MHz

× 10.9 V

= 0.000 W

WRx

× 44.7 pF

× 24 MHz

× 10.9 V

= 0.023 W

Data

× 14.7 pF

× 24 MHz

× 10.9 V

= 0.123 W

CLKOUT

× 4.7 pF

× 48 MHz

× 10.9 V

= 0.003 W
P

EXT

= 0.237 W

Figure 32. Output Enable/Disable

REFERENCE
SIGNAL

DIS

OUTPUT STARTS

DRIVING

(MEASURED) 

(MEASURED) +

MEASURED

(MEASURED)

2.0V

1.0V

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

OUTPUT STOPS

DRIVING

DECAY

ENA

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April 2002

PRELIMINARY TECHNICAL DATA

Capacitive Loading

Output delays and holds are based on standard capacitive
loads: 12 pF on all pins (see

Figure 33

Figure 35

and

Figure 36

show how output rise time varies with capaci-

tance.

Figure 37

graphically shows how output delays and

holds vary with load capacitance. (Note that this graph or
derating does not apply to output disable delays; see

Output

Disable Time on page 47

.) The graphs of

Figure 35

Figure 36

, and

Figure 37

may not be linear outside the

ranges shown.

Environmental Conditions

The ADSP-21160NKB-95 and ADSP-21160NCB-TBD
are provided in a 400-Ball Metric PBGA (Plastic Ball Grid
Array) package.

Thermal Characteristics

The ADSP-21160N is specified for a case temperature
(T

CASE

). To ensure that the T

CASE

data sheet specification is

not exceeded, a heatsink and/or an air flow source may be
used. Use the center block of ground pins (PBGA balls:
F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14,
P7-14, R7-15) to provide thermal pathways to the printed
circuit board's ground plane. A heatsink should be attached
to the ground plane (as close as possible to the thermal
pathways) with a thermal adhesive.

Figure 33. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Figure 34. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Figure 35. Typical Output Rise Time (10%90%,

DDEXT

= Max) vs. Load Capacitance

1.5V

12PF

OUTPUT

PIN

INPUT

OUTPUT

1.5V

LOAD CAPACITANCE pF

20.00

0.0

250

100

150

200

30.00

10.00

5.00

25.00

15.00

TBD

I
S

I
M

RISE TIME

FALL TIME

Y = 0.072781X

+ 1.99

Y = 0.086687X

+ 2.18

Figure 36. Typical Output Rise Time (10%90%,

DDEXT

= Min) vs. Load Capacitance

Figure 37. Typical Output Delay or Hold vs. Load

Capacitance (at Max Case Temperature)

LOAD CAPACITANCE pF

250

100

150

200

TBD

FALL TIME

Y = 0.076014X

2.15

Y = 0.086192X

+ 2.34

RISE TIME

LOAD CAPACITANCE pF

15.00

0.0

250

100

150

200

5.00

20.00

10.0

Y = 0.085526X

 3.87

REV. PrB

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April 2002

PRELIMINARY TECHNICAL DATA

Table 32. 400-ball Metric PBGA Pin Assignments

Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

DATA[14] A01

DATA[22]

B01

DATA[24]

C01

DATA[28]

D01

DATA[13] A02

DATA[16]

B02

DATA[18]

C02

DATA[25]

D02

DATA[10] A03

DATA[15]

B03

DATA[17]

C03

DATA[20]

D03

DATA[8]

A04

DATA[9]

B04

DATA[11]

C04

DATA[19]

D04

DATA[4]

A05

DATA[6]

B05

DATA[7]

C05

DATA[12]

D05

DATA[2]

A06

DATA[3]

B06

DATA[5]

C06

DDEXT

D06

TDI

A07

DATA[0]

B07

DATA[1]

C07

DDINT

D07

TRST

A08

TCK

B08

TMS

C08

DDEXT

D08

RESET

A09

EMU

B09

TD0

C09

DDEXT

D09

RPBA

A10

IRQ2

B10

IRQ1

C10

DDEXT

D10

IRQ0

A11

FLAG3

B11

FLAG2

C11

DDEXT

D11

FLAG1

A12

FLAG0

B12

C12

DDEXT

D12

TIMEXP

A13

B13

C13

DDINT

D13

A14

B14

TCLK1

C14

DDEXT

D14

A15

DT1

B15

DR1

C15

TFS0

D15

TFS1

A16

RCLK1

B16

DR0

C16

L1DAT[7]

D16

RFS1

A17

RFS0

B17

L0DAT[7]

C17

L0CLK

D17

RCLK0

A18

TCLK0

B18

L0DAT[6]

C18

L0DAT[3]

D18

DT0

A19

L0DAT[5]

B19

L0ACK

C19

L0DAT[1]

D19

L0DAT[4] A20

L0DAT[2]

B20

L0DAT[0]

C20

L1CLK

D20

DATA[30] E01

DATA[34]

F01

DATA[38]

G01

DATA[40]

H01

DATA[29] E02

DATA[33]

F02

DATA[35]

G02

DATA[39]

H02

DATA[23] E03

DATA[27]

F03

DATA[32]

G03

DATA[37]

H03

DATA[21] E04

DATA[26]

F04

DATA[31]

G04

DATA[36]

H04

DDEXT

E05

DDEXT

F05

DDEXT

G05

DDEXT

H05

DDINT

E06

DDINT

F06

DDINT

G06

DDINT

H06

DDINT

E07

GND

F07

GND

G07

GND

H07

DDINT

E08

GND

F08

GND

G08

GND

H08

DDINT

E09

GND

F09

GND

G09

GND

H09

DDINT

E10

GND

F10

GND

G10

GND

H10

GND

E11

GND

F11

GND

G11

GND

H11

DDINT

E12

GND

F12

GND

G12

GND

H12

DDINT

E13

GND

F13

GND

G13

GND

H13

DDINT

E14

GND

F14

GND

G14

GND

H14

DDINT

E15

DDINT

F15

DDINT

G15

DDINT

H15

DDEXT

E16

DDEXT

F16

DDEXT

G16

DDEXT

H16

L1DAT[6] E17

L1DAT[4]

F17

L1DAT[2]

G17

L2DAT[5]

H17

L1DAT[5] E18

L1DAT[3]

F18

L2DAT[6]

G18

L2ACK

H18

L1ACK

E19

L1DAT[0]

F19

L2DAT[4]

G19

L2DAT[3]

H19

L1DAT[1] E20

L2DAT[7]

F20

L2CLK

G20

L2DAT[1]

H20

DATA[44] J01

CLK_CFG_0 K01

CLKIN

L01

M01

DATA[43] J02

DATA[46]

K02

CLK_CFG_1 L02

CLK_CFG_3 M02

DATA[42] J03

DATA[45]

K03

AGND

L03

CLKOUT

M03

DATA[41] J04

DATA[47]

K04

CLK_CFG_2 L04

M04

DDEXT

J05

DDEXT

K05

DDEXT

L05

DDEXT

M05

DDINT

J06

DDINT

K06

DDINT

L06

DDINT

M06

GND

J07

GND

K07

GND

L07

GND

M07

GND

J08

GND

K08

GND

L08

GND

M08

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

GND

J09

GND

K09

GND

L09

GND

M09

GND

J10

GND

K10

GND

L10

GND

M10

GND

J11

GND

K11

GND

L11

GND

M11

GND

J12

GND

K12

GND

L12

GND

M12

GND

J13

GND

K13

GND

L13

GND

M13

GND

J14

GND

K14

GND

L14

GND

M14

DDINT

J15

DDINT

K15

DDINT

L15

DDINT

M15

DDEXT

J16

DDEXT

K16

DDEXT

L16

DDEXT

M16

L2DAT[2] J17

BR6

K17

BR2

L17

PAGE

M17

L2DAT[0] J18

BR5

K18

BR1

L18

SBTS

M18

HBG

J19

BR4

K19

ACK

L19

M19

HBR

J20

BR3

K20

REDY

L20

L3DAT[7]

M20

N01

DATA[49]

P01

DATA[53]

R01

DATA[56]

T01

N02

DATA[50]

P02

DATA[54]

R02

DATA[58]

T02

DATA[48] N03

DATA[52]

P03

DATA[57]

R03

DATA[59]

T03

DATA[51] N04

DATA[55]

P04

DATA[60]

R04

DATA[63]

T04

DDEXT

N05

DDEXT

P05

DDEXT

R05

DDEXT

T05

DDINT

N06

DDINT

P06

DDINT

R06

DDINT

T06

GND

N07

GND

P07

GND

R07

DDINT

T07

GND

N08

GND

P08

GND

R08

DDINT

T08

GND

N09

GND

P09

GND

R09

DDINT

T09

GND

N10

GND

P10

GND

R10

DDINT

T10

GND

N11

GND

P11

GND

R11

DDINT

T11

GND

N12

GND

P12

GND

R12

DDINT

T12

GND

N13

GND

P13

GND

R13

DDINT

T13

GND

N14

GND

P14

GND

R14

DDINT

T14

DDINT

N15

DDINT

P15

GND

R15

DDINT

T15

DDEXT

N16

DDEXT

P16

DDEXT

R16

DDEXT

T16

L3DAT[5] N17

L3DAT[2]

P17

L4DAT[5]

R17

L4DAT[3]

T17

L3DAT[6] N18

L3DAT[1]

P18

L4DAT[6]

R18

L4ACK

T18

L3DAT[4] N19

L3DAT[3]

P19

L4DAT[7]

R19

L4CLK

T19

L3CLK

N20

L3ACK

P20

L3DAT[0]

R20

L4DAT[4]

T20

DATA[61] U01

ADDR[4]

V01

ADDR[5]

W01

ADDR[8]

Y01

DATA[62] U02

ADDR[6]

V02

ADDR[9]

W02

ADDR[11]

Y02

ADDR[3] U03

ADDR[7]

V03

ADDR[12]

W03

ADDR[13]

Y03

ADDR[2] U04

ADDR[10]

V04

ADDR[15]

W04

ADDR[16]

Y04

DDEXT

U05

ADDR[14]

V05

ADDR[17]

W05

ADDR[19]

Y05

DDEXT

U06

ADDR[18]

V06

ADDR[20]

W06

ADDR[21]

Y06

DDEXT

U07

ADDR[22]

V07

ADDR[23]

W07

ADDR[24]

Y07

DDEXT

U08

ADDR[25]

V08

ADDR[26]

W08

ADDR[27]

Y08

DDEXT

U09

ADDR[28]

V09

ADDR[29]

W09

ADDR[30]

Y09

DDEXT

U10

ID0

V10

ID1

W10

ADDR[31]

Y10

DDEXT

U11

ADDR[1]

V11

ADDR[0]

W11

ID2

Y11

DDEXT

U12

MS1

V12

BMS

W12

BRST

Y12

DDEXT

U13

V13

MS2

W13

MS0

Y13

DDEXT

U14

RDL

V14

CIF

W14

MS3

Y14

DDEXT

U15

DMAR2

V15

RDH

W15

WRH

Y15

DDEXT

U16

L5DAT[0]

V16

DMAG2

W16

WRL

Y16

L5DAT[7] U17

L5DAT[2]

V17

LBOOT

W17

DMAG1

Y17

Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

L4DAT[0] U18

L5ACK

V18

L5DAT[1]

W18

DMAR1

Y18

L4DAT[1] U19

L5DAT[4]

V19

L5DAT[3]

W19

EBOOT

Y19

L4DAT[2] U20

L5DAT[6]

V20

L5DAT[5]

W20

L5CLK

Y20

400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY)

Table 32. 400-ball Metric PBGA Pin Assignments (Continued)

Pin Name PBGA Pin# Pin Name

PBGA Pin# Pin Name

PBGA Pin#

DDINT

DDEXT

GND*

AGND

NO CONNECTION

I/O SIGNALS

K EY :

* USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: F7-14, G7-14, H7-14, J7-14,

K7-14, L7-14, M7-14, N7-14, P7-14, R7-15) TO PROVIDE THERMAL PATHWAYS TO YOUR
PRINTED CIRCUIT BOARD'S GROUND PLANE.

VDD

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

OUTLINE DIMENSIONS

The ADSP-21160N comes in a 27mm

27mm, 400-ball

Metric PBGA package with 20 rows of balls.

ORDERING GUIDE

400-BALL METRIC PBGA (B-400)

Part Number

B = Plastic Ball Grid Array (PBGA) package.

Case Temperature
Range

Instruction Rate

On-Chip
SRAM

Operating Voltage

ADSP-21160NCB-TBD

40°C to 100°C

TBD MHz

4M bits

1.9 INT/3.3 EXT V

ADSP-21160NKB-95

0°C to 85°C

95 MHz

4M bits

1.9 INT/3.3 EXT V

0.90

0.75

0.60

BALL DIAMETER

0.70

0.60

0.50

0.60

0.55

0.50

2.49

2.32

2.15

15 13

24.13

BSC

24.10

24.00

23.90

TOP VIEW

DETAIL A

NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS, EXCEPT (0.050) DIMENSION AT
BALL

PITCH IS IN INCHES.

2. CENTER FIGURES ARE NOMINAL DIMENSIONS.
3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30 OF ITS IDEAL

POSITION RELATIVE TO THE PACKAGE EDGES.

4. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.15 OF ITS IDEAL

POSITION RELATIVE TO THE BALL GRID.

SEATING

PLANE

1.19

1.17

1.15

0.20 MAX

DETAIL A

27.20

27.00

26.80

1.27 (0.050)

BSC

BALL PITCH

BOTTOM VIEW

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-21160N

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-21160N